HCLTech is a global technology company, home to more than224,756 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues US$ 13.1 Bn, for 12 Months Ended December 31, 2023. To learn how we can supercharge progress for you, visit https://www.hcltech.com/

Roles and Responsibilities:

• To be responsible for managing technology in projects and providing technical guidance / solutions for work completion.
• To be responsible for providing technical guidance / solutions.
• To develop and guide the team members in enhancing their technical capabilities and increasing productivity.
• To ensure process compliance in the assigned module| and participate in technical discussions/review.
• To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations.

Experience/Exposure:

• Professional experience of executing physical design projects from 5 years of experience.
• Proven ability in technically leading a small/medium size team for executing projects preferred
• Hands on experience on the entire PD Flow from RTL to GDSII
• Should have good understanding of Floor planning, Power Planning, Placement & Optimization, CTS, Routing, Design Convergence and Sign-off with in depth expertise in at least one of these domains
• Working knowledge about OCV, MM/MC optimization and multi power designs (Level shifters, Isolation cells etc)
• Exposure to static timing analysis fixes including automated ECO generation
• Strong in areas on CTS and skew fixing
• Library preparation in any environment (Synopsys, Cadence etc)
• Working knowledge on Physical verifications tasks at lower nodes (data base merging/DRC/LVS/ERC/PERC/Antenna/ESD/LUP analysis/fixing ) at block level/chip level
• Job would require complete ownership from netlist/RTL to GDS for blocks at Block level OR full chip level
• Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage
• Working knowledge of scripting language like Perl, TCL will be considered a plus
• Candidate needs to be self-driven and confident in reporting out status and sharing technical results with customers
• Must have the ability to present to senior management, work in a geographically dispersed team and be aware of cross-cultural nuances
• Should be able to define project milestones, identify risks and call out mitigation plans

Preferred Qualifications:

• University or College

Required Skills:

• Physical Design
• Place and Route
• STA
• RTL