Qualification Required:

• Typically requires minimum of 6-10 years of experience in Physical Design with mainstream P&R tools.
• Bachelors OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.

Roles And Responsibilities

• Multiple tapeout experience in full chip PnR for lower node technologies. Intel flow experience is good to have on Cheetah 2.0/HDK
• Experience in ICC2/Innovus/DC tools, Fusion compiler being added advantage.
• Experience in ETM/QTM based full chip PnR including synthesis.
• Full chip CTS methodology planning/implementation.
• Experience in closure of complex block PnR implementation.
• Experience in low power design implementation, CLP checks.
• Experience in independently setting up equivalency check runs including full chip.
• Experience in interfacing with cross functional teams and block PnR teams.
• Good understanding of basic shell scripting, tool based TCL scripting to automate all custom activities.
• Experience leading team of significant strength.
• Experience in version control systems.
• Experience in managing/mentoring small teams

Required Technical And Professional Expertise:

• Excellent communication and interpersonal skills.
• Strong and effective presentation skills, able to operate at multiple levels including senior management
• Self-motivated
• Take ownership of problems
• Creative problem solving
• Team player