Qualification Required:

• Typically requires minimum of 5-10 years of experience in DFT on high complexity SoC designs.
• Bachelors OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.

Roles And Responsibilities

• 5+ Experience in complex SOC level DFT execution in advanced finFET technology.
• Strong DFT fundamental knowledge from defect models to ATPG algorithm.
• Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent.
• Knowledge of basic SoC architecture and HDL languages like Verilog to be able to work with logic design teams for timing fixes

Required Technical And Professional Expertise:

• Excellent communication and interpersonal skills.
• Strong and effective presentation skills, able to operate at multiple levels including senior management.
• Self-motivated.
• Take ownership of problems.
• Creative problem solving.
• Team player