Qualification Required:

• Typically requires minimum of 4-10 years of experience in Analog Layout with PCELL Extraction and people management knowledge.
• Bachelors OR Master’s Degree Engineering in Electronics or Electrical or VLSI Engineering.

Roles And Responsibilities:

• Work experience on Custom Layout Design, Physical Verifications (DRC, LVS, Antenna) & Extraction.
• Good understanding of CMOS & Analog Layout fundamentals.
• Knowledge on PCELL creation is preferred.
• Team/Project Management experience is preferred.
• Good oral & written communication skills.