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Physical Design Engineer
Qualification Required:
- Typically requires minimum of 4-10 years of experience in Physical Design with mainstream P&R tools
- Bachelors OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.
Roles And Responsibilities
- Working on 10nm/7nm/5nm or lower nodes designs with various customers for deployment.
- Expertise in solving customer's problems for critical designs to achieve desired performance, area, and power targets.
- Responsible to develop flow and methodology for doing placement, CTS, and routing.
- Provide training and technical support to customers
Required Technical And Professional Expertise:
- Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations). Experience on hierarchical designs and/or Low Power implementation is an advantage.
- Experience on Synthesis, interfacing with RTL and implementation designers to achieve better quality of results.
- Experience on Floorplan design, including placement of hard macros, padring, power grid and custom analog routes.
- Experience on Static Timing Analysis related activities (constraints development, parasitic extractions, sign-off requirements).
- Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing).
- Hands-on experience with FinFET technologies is an advantage
Compensation and Benefits
A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year.